1. Field
An embodiment of the present invention relates to the field of integrated circuit design and, more particularly, to the design of on-chip clock generation circuits.
2. Discussion of Related Art
Many modern integrated circuit devices, such as microprocessors, for example, use an on-chip phase locked loop (PLL) to synthesize a core clock signal. The core clock signal is then distributed across the device for use by various units. Such on-chip clock generation is advantageous in terms of hiding on-chip clock delays from external devices and in providing an efficient approach for clock frequency multiplication.
An example of a processor 100 including a prior on-chip clock generator unit 105 is shown in FIG. 1. At an input/output unit 110, an external clock signal 115 is received at a pin, for example, of the processor device 100. The external clock signal 115 is routed to an input of a PLL 120 in the clock generator unit 105. A PLL feedback clock signal 125 is also received by the PLL 120 to provide phase locked operation.
An output clock signal from the PLL 120 is buffered by one or more buffers 130 and provided as a core clock signal 135 through a clock distribution network 138 (only one signal line of which is shown) to various locations across the processor 100 including a bus clock generator 140. The bus clock generator 140 is provided to generate a clock signal for clocking external bus transactions. This clock signal may also be used as the PLL feedback clock signal 120.
The on-chip clock circuit of FIG. 1 may have some disadvantages, however, particularly when used on a large die, such as a microprocessor, in a high performance environment. The PLL feedback clock signal 120 is typically generated in the input/output area of a device. This input/output area is usually located near the periphery of a die for performance reasons.
The core clock signal 135 is delivered from the clock generator unit 105 to the input/output unit 110 by the above-mentioned clock distribution network including the signal line 138 shown in FIG. 1. Because the clock generator unit 105 provides the core clock signal to locations all over the processor 100, the clock generator unit is often located near the center of the die to facilitate distribution of the signal. Thus, particularly for a large die, the core clock signal 135 may traverse a relatively long distance across the processor 100, before reaching the bus clock generator 140.
As the core clock signal 135 is communicated from the clock generator unit 105 to the input/output unit 110 through various areas of the processor 100, such as the units 1 . . . n, the signal 135 is susceptible to localized power supply noise and signal cross-coupling in various regions. This noise is difficult to control due to the various activity and circuitry types across the processor 100 and may result in delay variation in the core clock signal 135 as it arrives at the bus clock generator 140. Because the PLL feedback clock signal 120 used to generate the core clock signal 135 is derived by the bus clock generator 140 from this core clock input signal 135, such delay variation may lead to clock jitter of the core clock signal 135.
Clock jitter can directly affect the overall performance of the processor 100 by effectively reducing the input/output (I/O) bus transaction rate. Because jitter results in a variation in clock edge placement, the bus transaction rate is reduced to account for this variation.
Other types of integrated circuit devices, such as digital signal processors, communications chips, cache memories, etc. that use on-die clock generators may present similar issues.